View HD74ALVCH16501_5117818.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HD74ALVCH16501 18-bit universal bus transceivers with 3-state outputs ade-205-168a (z) 2nd. edition december 1999 description data flow in each direction is controlled by output enable (oeab and oeba ), latch enable (leab and leba), and clock (clkab and clkba) inputs. for a to b data flow, the device operates in the transparent mode when leab is high. when leab is low, the a data is latched if clkab is held at a high or low logic level. if leab is low, the a bus data is stored in the latch flip flop on the low to high transition of clkab. when oeab is high, the outputs are active. when oeab is low, the outputs are in the high impedance state. data flow for b to a is similar to that of a to b but uses oeba , leba, and clkba. the output enables are complementary (oeab is active high, and oeba is active low). active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. features v cc = 2.3 v to 3.6 v typical v ol ground bounce < 0.8 v (@v cc = 3.3 v, ta = 25 c) typical v oh undershoot > 2.0 v (@v cc = 3.3 v, ta = 25 c) high output current 24 ma (@v cc = 3.0 v) bus hold on data inputs eliminates the need for external pullup / pulldown resistors
HD74ALVCH16501 2 function table *3 inputs output b oeab leab clkab a l xxxz hhxl l hhxhh hl - ll hl - hh hl hxb 0 *1 hllxb 0 *2 h : high level l : low level x : immaterial z : high impedance - : low to high transition notes: 1. output level before the indicated steady state input conditions were established. 2. output level before the indicated steady state input conditions were established, provided that clkab was high before leab went low. 3. a to b data flow is show; b to a flow is similar but uses oeba , leba, and clkba.
HD74ALVCH16501 3 pin arrangement (top view) 1 2 3 4 5 6 7 8 9 10 v cc v cc leab a1 gnd a2 a3 a4 a5 a6 gnd a7 a8 a9 a10 a11 a12 gnd a13 a14 a15 a16 a17 oeab 11 12 13 14 15 16 17 18 19 20 21 22 23 24 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 b17 gnd 25 32 gnd a18 26 31 b18 oeba 27 30 clkba leba 28 29 gnd b16 b15 b14 b13 b12 gnd b11 b10 b9 b8 b7 gnd b6 b5 b4 b3 b2 b1 gnd gnd clkab v cc v cc
HD74ALVCH16501 4 absolute maximum ratings item symbol ratings unit conditions supply voltage v cc ?.5 to 4.6 v input voltage *1, 2 v i ?.5 to 4.6 v except i/o ports ?.5 to v cc +0.5 i/o ports output voltage *1, 2 v o ?.5 to v cc +0.5 v input clamp current i ik ?0 ma v i < 0 output clamp current i ok 50 ma v o < 0 or v o > v cc continuous output current i o 50 ma v o = 0 to v cc 100 maximum power dissipation at ta = 55 c (in still air) *3 p t 1 w tssop storage temperature tstg ?5 to 150 c notes: stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ?ecommended operating conditions?is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. the input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. this value is limited to 4.6 v maximum. 3. the maximum package power dissipation is calculated using a junction temperature of 150 c and a board trace length of 750 mils. recommended operating conditions item symbol min max unit conditions supply voltage v cc 2.3 3.6 v input voltage v i 0v cc v output voltage v o 0v cc v high level output current i oh ?2 ma v cc = 2.3 v ?2 v cc = 2.7 v ?4 v cc = 3.0 v low level output current i ol ?2mav cc = 2.3 v ?2 v cc = 2.7 v ?4 v cc = 3.0 v input transition rise or fall rate d t / d v 0 10 ns / v operating temperature ta ?0 85 c note: unused control inputs must be held high or low to prevent them from floating.
HD74ALVCH16501 5 logic diagram clk c1 1d clk c1 1d oeab clkab leba clkba b1 leab 1 54 55 2 28 30 oeba 27 a1 3 to seventeen other channels
HD74ALVCH16501 6 electrical characteristics (ta = ?0 to 85 c) item symbol v cc (v) *1 min max unit test conditions input voltage v ih 2.3 to 2.7 1.7 v 2.7 to 3.6 2.0 v il 2.3 to 2.7 0.7 2.7 to 3.6 0.8 output voltage v oh min to max v cc ?.2 v i oh = ?00 m a 2.3 2.0 i oh = ? ma, v ih = 1.7 v 2.3 1.7 i oh = ?2 ma, v ih = 1.7 v 2.7 2.2 i oh = ?2 ma, v ih = 2.0 v 3.0 2.4 i oh = ?2 ma, v ih = 2.0 v 3.0 2.0 i oh = ?4 ma, v ih = 2.0 v v ol min to max 0.2 i ol = 100 m a 2.3 0.4 i ol = 6 ma, v il = 0.7 v 2.3 0.7 i ol = 12 ma, v il = 0.7 v 2.7 0.4 i ol = 12 ma, v il = 0.8 v 3.0 0.55 i ol = 24 ma, v il = 0.8 v input current i in 3.6 5 m av in = v cc or gnd i in (hold) 2.3 45 v in = 0.7 v 2.3 ?5 v in = 1.7 v 3.0 75 v in = 0.8 v 3.0 ?5 v in = 2.0 v 3.6 500 v in = 0 to 3.6 v off state output current *2 i oz 3.6 10 m av out = v cc or gnd quiescent supply current i cc 3.6 40 m av in = v cc or gnd d i cc 3.0 to 3.6 750 m av in = one input at (v cc ?.6) v, other inputs at v cc or gnd notes: 1. for conditions shown as min or max, use the appropriate values under recommended operating conditions. 2. for i/o ports, the parameter i oz includes the input leakage current.
HD74ALVCH16501 7 switching characteristics (ta = ?0 to 85 c) item symbol v cc (v) min typ max unit from (input) to (output) maximum clock frequency f max 2.5 0.2 150 mhz 2.7 150 3.3 0.3 150 propagation delay time t plh 2.5 0.2 1.2 4.8 ns a or b b or a t phl 2.7 4.5 3.3 0.3 1.0 3.9 2.5 0.2 1.6 5.7 le a or b 2.7 5.3 3.3 0.3 1.3 4.6 2.5 0.2 1.7 6.1 clk a or b 2.7 5.6 3.3 0.3 1.4 4.9 output enable time t zh 2.5 0.2 1.1 5.8 ns oeab b t zl 2.7 5.3 3.3 0.3 1.0 4.6 2.5 0.2 1.4 6.3 oeba a 2.7 6.0 3.3 0.3 1.1 5.0 output disable time t hz 2.5 0.2 2.2 6.2 ns oeab b t lz 2.7 5.7 3.3 0.3 1.4 5.0 2.5 0.2 2.0 5.3 oeba a 2.7 4.6 3.3 0.3 1.3 4.2 input capacitance c in 3.3 4.0 pf control inputs output capacitance c in / o 3.3 8.0 pf a or b ports
HD74ALVCH16501 8 switching characteristics (ta = ?0 to 85 c) (cont) item symbol v cc (v) min typ max unit from (input) setup time t su 2.5 0.2 2.2 ns data before clk - 2.7 2.1 3.3 0.3 1.7 2.5 0.2 1.9 data before le 2.7 1.6 clk ? 3.3 0.3 1.5 2.5 0.2 1.3 data before le 2.7 1.1 clk ? 3.3 0.3 1.0 hold time t h 2.5 0.2 0.6 ns data after clk - 2.7 0.6 3.3 0.3 0.7 2.5 0.2 1.4 data after le 2.7 1.7 clk ??or ? 3.3 0.3 1.4 pulse width t w 2.5 0.2 3.3 ns le ? 2.7 3.3 3.3 0.3 3.3 2.5 0.2 3.3 clk ??or ? 2.7 3.3 3.3 0.3 3.3
HD74ALVCH16501 9 500 w c = 50 pf l l 500 w s1 *1 see under table gnd open load circuit for outputs note: 1. c includes probe and jig capacitance. symbol t / t plh phl open gnd 4.6 v 6.0 v t / t zh hz t / t zl lz t / t / t su h w open gnd vcc=2.7v, 3.3 0.3v vcc=2.5 0.2v ?test circuit
HD74ALVCH16501 10 t plh t phl t su t h v oh v ol t w gnd v ih gnd v ih gnd v ih gnd v ih v ref v ref v ref v ref v ref v ref v ref v ref v ref input output timing input data input input ?waveforms ?1 ?waveforms ?2 10 % 90 % tr tf 10 % 90 % 10 % 90 % tr
HD74ALVCH16501 11 v ?0.3 v oh v + 0.3 v ol t zl t lz t zh t hz v oh v ol waveform - a output control waveform - b gnd v ih ? v ol1 ? v oh1 v ref v ref v ref v ref test v ih v ref v oh1 v ol1 1.2 v 1.5 v 2.3 v 3.0 v gnd 2.3 v 2.7 v gnd vcc=2.7v, 3.3 0.3v vcc=2.5 0.2v notes: 1. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, zo = 50 w , tr 2.5 ns, tf 2.5 ns. 2. waveform ?a is for an output with internal conditions such that the output is low except when disabled by the output control. 3. waveform ?b is for an output with internal conditions such that the output is high except when disabled by the output control. 4. the output are measured one at a time with one transition per measurement. ?waveforms ?3 tr tf 10 % 10 % 90 % 90 %
HD74ALVCH16501 12 package dimensions unit : mm hitachi code eiaj code jedec code ttp-56d 0.08 m 0.10 0.20 0.15 0.05 8.10 0.3 0.40 max 128 29 56 +0.1 ?.05 +0.3 ?.1 14.00 +0.3 ?.1 6.10 1.20 max 10 max 0.50 0.05 min 0.50 0.1
HD74ALVCH16501 13 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ? hitachi, ltd., 1999. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/index.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher strae 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

▲Up To Search▲

Price & Availability of HD74ALVCH16501

	To Download HD74ALVCH16501 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .